The present invention relates to semiconductor devices, and more particularly to a vertically oriented field effect transistor (FET) which includes a dog-bone structure. The present invention also relates to a method of fabricating the aforementioned vertically oriented FET.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., xe2x80x9cScaling the Si MOSFET: From bulk to SOI to bulkxe2x80x9d, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for subxe2x88x920.05 Âxcexcm MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of a typical prior art double-gated MOSFET consists of a very thin vertical Si layer (Fin) for the channel, with two gates, one on each side of the channel. The term xe2x80x9cFinxe2x80x9d is used herein to denote a semiconducting material which is employed as the body of the FET. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
For FinFET CMOS (complementary metal oxide semiconductor) applications, it is beneficial to provide a structure that has the thinnest single crystal silicon Fin possible for the device body. However, this makes contacting of the source and drain regions quite difficult. Optimally, the device portion of the Fin is quite thin, with the source and drain regions being thicker, in order to facilitate silicide growth and metal contact schemes.
Jong-Ho Lee, et al. xe2x80x9cSuper Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxyxe2x80x9d, 1999 IEEE International Devices Meeting (IEDM) Technical Digest-International Electron Devices Meeting, pp. 71-74, provide a self-aligned double-gate MOSFET structure that reportedly has low source/drain resistance which should lead to increased current. The structure disclosed in the Jong-Ho Lee, et al. article (See, in particular FIGS. 1(e), (f), (exe2x80x2) and (fxe2x80x2)) contains a thin channel region and wider source/drain regions abutting the channel region. In the disclosed structure, the transition in widths between the channel region and both the source and drain regions is abrupt; therefore the disclosed structure will have an overlap capacitance which is high. It should also be pointed out that in this prior art structure, the thin/thick dimensions between the channel and source/drain regions are in the vertical direction.
In view of the above drawbacks with prior art FinFET structures, there is a continued need for providing a structure in which the FET includes source/drain regions that have a wider width than the width of the abutting channel region where the transition in widths between the channel region and the source/drain regions is not abrupt.
One object of the present invention is to provide a vertically oriented FET which has a dog-bone structure which includes a channel region and wider source/drain regions that abut the channel region.
Another object of the present invention is to provide a vertically oriented FET which has a dog-bone structure in which the source/drain regions are tapered from the channel region thereby avoiding high overlap capacitance that is typically caused by an abrupt transition in widths between the channel region and the abutting source/drain regions.
A further object of the present invention is to provide a vertically oriented FET in which the source/drain regions abutting the channel region have tapered portions with a horizontal width that varies in a substantially linear manner.
A still further object of the present invention is to provide a vertically oriented FET which has a self-aligned dog-bone structure.
An even further object of the present invention is to provide a method of fabricating a self-aligned dog-bone structure for a FinFET structure which implements existing CMOS technologies.
These and other objects and advantages are achieved in the present invention by providing a vertically oriented FET structure having a thin channel region and abutting thick source/drain regions wherein the portions between the source/drain regions and the channel region are tapered in a substantially linear manner. The linear tapering avoids abrupt transitions in width between the thin channel region and the thicker, abutting source/drain regions.
Specifically, and in one aspect of the present invention, the present invention relates to a vertically oriented FET comprising:
a channel region, a source region and a drain region, said channel region having a first horizontal width and said source and drain regions having a second horizontal width that is greater than said first horizontal width, each of said source and drain regions having tapered portions abutting said channel region with a horizontal width that varies in a substantially linear manner from said first horizontal width to said second horizontal width.
Another aspect of the present invention relates to a method of fabricating the inventive vertically oriented FET structure. Specifically, the method of the present invention comprises the steps of:
providing a structure including at least one patterned semiconducting body region, said at least one patterned semiconducting body region is present atop an insulating layer; and
etching said patterned semiconducting body region to form a first region, a second region and a third region, said first region having a first horizontal width and said second and third regions having a second horizontal width that is greater than said first horizontal width, each of said second and third regions having tapered portions abutting said first region with a horizontal width that varies in a substantially linear manner from said first horizontal width to said second horizontal width.
It is emphasized that the term xe2x80x9cdog-bonexe2x80x9d is used herein to describe the etched, patterned semiconductor body region which includes the first (i.e., channel), second and third (i.e., source/drain) regions mentioned above. The inventive dog-bone structure differs from typical prior art dog-bone configurations in that the portions between the thicker second and third regions and the channel region are tapered in a substantially linear manner. Such tapering prevents the structure from exhibiting high overlap capacitance.